|
The interrupter generates the signal which drives the resonant circuit (coil rig) at its resonant frequency $f_0$. As long as the input signal X2 is active the output is driven at the resonant frequency $f_0$. It does this by the means of a positive feedback loop. The feedback signal X8 is retrieved with a sensing transformer around the output wire from the power amplifier, before being clamped, rectified, and schmidt triggered. The positive flanks of this signal represents when the output current passes zero (this is when we want to switch the polarity of the output). This signal is fed to the output via gates controlled by a latch, the signal to one of the outputs is inverted (for push-pull operation).
|
|
The interrupter generates the signal which drives the resonant circuit (coil rig) at its resonant frequency $f_0$. As long as the input signal X2 is active the output is driven at the resonant frequency $f_0$. It does this by the means of a positive feedback loop. The feedback signal X8 is retrieved with a sensing transformer around the output wire from the power amplifier, before being clamped, rectified, and schmidt triggered. The positive flanks of this signal represents when the output current passes zero (this is when we want to switch the polarity of the output). This signal is fed to the output via gates controlled by a latch, the signal to one of the outputs is inverted (for push-pull operation).
|
|
|
|
|
|
D3-D6 are protection diodes which clamp the feedback signal to safe voltages. The network L1 and R2 introduces a tunable phase lead on the voltage. Since we are detecting when the current |
|
D3-D6 are protection diodes which clamp the feedback signal to safe voltages. The network L1 and R2 introduces a tunable phase lead on the voltage. C1 and R1 is a filter to remove noise. D1 and D2 clamps the voltage to 0-5V.
|
|
\ No newline at end of file |
|
|
|
|
|
Initially no current is flowing in the resonant circuit therefore no voltage is present on X8 and the input U2A is low. Pin 1 of U3A is low and pin 4 of U1B is high. And the clock input of the latch (U1A) is high. Reset is low. When X2 goes high the SD (Set Data) input of the latch (U1A) is activated, reset (RD) goes low, and the output (Q) goes high. Then X4B goes high and causes a step response in the resonant circuit. The feedback transformer is oriented such that this current direction gives a negative voltage on X8 and thus still low signal on the input of U2A. When the current direction changes the signal on the input of U2A goes from low to high and X4A goes high and X4B goes low. This reverses the voltage on the resonant circuit in phase with the step response and triggers an additional step response in phase with the already ongoing one. This cycle continues until X2 goes low. When X2 goes low SD goes low, but Q is still high until the next negative flank on X8 (inverted through U2A). When D (wich is strapped low) is clocked through the latch. and Q goes low and both X4A and X4B goes low. And no further energy is supplied to the resonant circuit and the step response completes.
|
|
|
|
|
|
|
|
The function of L1 and R2 is to introduce a phase lead on the voltage of X8 in relation of the current on X8. This is so that one can compensate for delays in the circuit. When the circuit is inductive the voltage will lead the current. By adjusting the value of R2 the relation between the inductance and resistance is changed and thus the phase angle is changed. And the time between the voltage crosses zero and the current crosses zero can be adjusted. This time should be equal to the time it takes the feedback signal X8 to propagate through the logic and for the IGBT to turn on or off. So that we will switch when the current in the resonant circuit is zero (Zero current switching). This is to reduce energy lost from the resonant circuit and to minimize power burned in the transistors (when switching).
|
|
|
|
|
|
|
|
The function of the network connected to the reset (RD) of the latch (U1A) is to reset the latch after a delay in the case that a zero crossing is not detected on X8 after X2 goes low. When X2 goes high the input of U2D goes low immediately due to the capacitor C2 being discharged through D7, but when X2 goes low the capacitor will be charged through R3 and there will be a delay before the latch is reset. |
|
|
|
\ No newline at end of file |