Commit fb3d1624 authored by insult's avatar insult
Browse files

Tegnet på kraftforsyning

Komponentene er ikke nødvendigvis de som er brukt eller har riktig kjøpsinfo
parent e6efb7c1
------------------------------------------------------------
-- VHDL TK500_Driver
-- 2014 7 12 23 24 4
-- 2015 7 5 14 55 23
-- Created By "DXP VHDL Generator"
-- "Copyright (c) 2002-2014 Altium Limited"
-- Product Version: 14.3.11.33708
-- Product Version: 15.0.7.36915
------------------------------------------------------------
------------------------------------------------------------
......@@ -185,11 +185,13 @@ Architecture Structure Of TK500_Driver Is
Component TK525_Kraftforsyning -- ObjectKind=Sheet Symbol|PrimaryId=TK525
port
(
AC_S6 : inout STD_LOGIC; -- ObjectKind=Sheet Entry|PrimaryId=TK525_Kraftforsyning.SchDoc-AC_S6
AC_S7 : inout STD_LOGIC; -- ObjectKind=Sheet Entry|PrimaryId=TK525_Kraftforsyning.SchDoc-AC_S7
AC_S8 : inout STD_LOGIC; -- ObjectKind=Sheet Entry|PrimaryId=TK525_Kraftforsyning.SchDoc-AC_S8
GND_HV : out STD_LOGIC; -- ObjectKind=Sheet Entry|PrimaryId=TK525_Kraftforsyning.SchDoc-GND_HV
P160V : out STD_LOGIC -- ObjectKind=Sheet Entry|PrimaryId=TK525_Kraftforsyning.SchDoc-P160V
AC_S6 : inout STD_LOGIC; -- ObjectKind=Sheet Entry|PrimaryId=TK525_Kraftforsyning.SchDoc-AC_S6
AC_S7 : inout STD_LOGIC; -- ObjectKind=Sheet Entry|PrimaryId=TK525_Kraftforsyning.SchDoc-AC_S7
AC_S8 : inout STD_LOGIC; -- ObjectKind=Sheet Entry|PrimaryId=TK525_Kraftforsyning.SchDoc-AC_S8
GND_HV : out STD_LOGIC; -- ObjectKind=Sheet Entry|PrimaryId=TK525_Kraftforsyning.SchDoc-GND_HV
L1_230VAC : in STD_LOGIC; -- ObjectKind=Sheet Entry|PrimaryId=TK525_Kraftforsyning.SchDoc-L1_230VAC
L2_230VAC : in STD_LOGIC; -- ObjectKind=Sheet Entry|PrimaryId=TK525_Kraftforsyning.SchDoc-L2_230VAC
P160V : out STD_LOGIC -- ObjectKind=Sheet Entry|PrimaryId=TK525_Kraftforsyning.SchDoc-P160V
);
End Component;
......
------------------------------------------------------------
-- VHDL TK510_Signalbakplan
-- 2014 7 12 23 23 56
-- 2015 7 5 14 55 25
-- Created By "DXP VHDL Generator"
-- "Copyright (c) 2002-2014 Altium Limited"
-- Product Version: 14.3.11.33708
-- Product Version: 15.0.7.36915
------------------------------------------------------------
------------------------------------------------------------
......@@ -212,6 +212,9 @@ Architecture Structure Of TK510_Signalbakplan Is
Component TK510_Mekanisk -- ObjectKind=Sheet Symbol|PrimaryId=TK510
End Component;
Component TK510_VCCMINUSKontakter -- ObjectKind=Sheet Symbol|PrimaryId=VCC_CONN
End Component;
Component TSM2314 -- ObjectKind=Part|PrimaryId=Q51000|SecondaryId=1
port
(
......@@ -1659,6 +1662,9 @@ Architecture Structure Of TK510_Signalbakplan Is
Begin
VCC_CONN : TK510_VCCMINUSKontakter -- ObjectKind=Sheet Symbol|PrimaryId=VCC_CONN
;
TK510 : TK510_Mekanisk -- ObjectKind=Sheet Symbol|PrimaryId=TK510
;
......
------------------------------------------------------------
-- VHDL TK511_Blindkort
-- 2014 7 12 23 24 5
-- 2015 7 5 14 55 24
-- Created By "DXP VHDL Generator"
-- "Copyright (c) 2002-2014 Altium Limited"
-- Product Version: 14.3.11.33708
-- Product Version: 15.0.7.36915
------------------------------------------------------------
------------------------------------------------------------
......@@ -14,37 +14,6 @@ Library IEEE;
Use IEEE.std_logic_1164.all;
Entity TK511_Blindkort Is
port
(
A1 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=A1
A2 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=A2
A3 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=A3
A4 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=A4
A5 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=A5
A6 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=A6
A7 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=A7
A8 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=A8
A9 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=A9
B3 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=B3
B4 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=B4
B5 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=B5
B6 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=B6
B7 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=B7
B8 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=B8
B9 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=B9
B10 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=B10
B11 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=B11
B12 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=B12
B13 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=B13
B14 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=B14
FEIL : Out STD_LOGIC; -- ObjectKind=Port|PrimaryId=FEIL
INTERRUPT : Out STD_LOGIC; -- ObjectKind=Port|PrimaryId=INTERRUPT
KORT_INNSATT : Out STD_LOGIC; -- ObjectKind=Port|PrimaryId=KORT INNSATT
LIMIT : In STD_LOGIC; -- ObjectKind=Port|PrimaryId=LIMIT
RESERVELED : Out STD_LOGIC; -- ObjectKind=Port|PrimaryId=RESERVELED
STATUS : Out STD_LOGIC; -- ObjectKind=Port|PrimaryId=STATUS
TRIGGER : In STD_LOGIC -- ObjectKind=Port|PrimaryId=TRIGGER
);
attribute MacroCell : boolean;
End TK511_Blindkort;
......@@ -52,9 +21,129 @@ End TK511_Blindkort;
------------------------------------------------------------
Architecture Structure Of TK511_Blindkort Is
Component PCIeX1MINUSGFMINUS2DMINUS1000MINUS1KMINUSO36 -- ObjectKind=Part|PrimaryId=J51100|SecondaryId=1
port
(
A1 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=J51100-A1
A2 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=J51100-A2
A3 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=J51100-A3
A4 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=J51100-A4
A5 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=J51100-A5
A6 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=J51100-A6
A7 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=J51100-A7
A8 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=J51100-A8
A9 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=J51100-A9
A10 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=J51100-A10
A11 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=J51100-A11
A12 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=J51100-A12
A13 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=J51100-A13
A14 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=J51100-A14
A15 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=J51100-A15
A16 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=J51100-A16
A17 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=J51100-A17
A18 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=J51100-A18
B1 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=J51100-B1
B2 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=J51100-B2
B3 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=J51100-B3
B4 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=J51100-B4
B5 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=J51100-B5
B6 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=J51100-B6
B7 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=J51100-B7
B8 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=J51100-B8
B9 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=J51100-B9
B10 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=J51100-B10
B11 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=J51100-B11
B12 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=J51100-B12
B13 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=J51100-B13
B14 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=J51100-B14
B15 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=J51100-B15
B16 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=J51100-B16
B17 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=J51100-B17
B18 : inout STD_LOGIC -- ObjectKind=Pin|PrimaryId=J51100-B18
);
End Component;
Signal NamedSignal_B10 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=B10
Signal NamedSignal_B11 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=B11
Signal NamedSignal_B12 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=B12
Signal NamedSignal_B13 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=B13
Signal NamedSignal_B14 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=B14
Signal NamedSignal_B5 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=B5
Signal NamedSignal_B6 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=B6
Signal NamedSignal_B7 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=B7
Signal NamedSignal_B8 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=B8
Signal NamedSignal_B9 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=B9
Signal NamedSignal_INTERRUPT : STD_LOGIC; -- ObjectKind=Net|PrimaryId=INTERRUPT
Signal NamedSignal_KORT_INNSATT : STD_LOGIC; -- ObjectKind=Net|PrimaryId=KORT_INNSATT
Signal NamedSignal_LIMIT : STD_LOGIC; -- ObjectKind=Net|PrimaryId=LIMIT
Signal NamedSignal_TRIGGER : STD_LOGIC; -- ObjectKind=Net|PrimaryId=TRIGGER
Signal PowerSignal_GND : STD_LOGIC; -- ObjectKind=Net|PrimaryId=GND
Signal PowerSignal_VCC_EXTRA : STD_LOGIC; -- ObjectKind=Net|PrimaryId=VCC_EXTRA
Signal PowerSignal_VCC_P18V : STD_LOGIC; -- ObjectKind=Net|PrimaryId=VCC_P18V
Signal PowerSignal_VCC_P5V0 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=VCC_P5V0
attribute Database_Table_Name : string;
attribute Database_Table_Name of J51100 : Label is "altium";
attribute id : string;
attribute id of J51100 : Label is "3177";
attribute navn : string;
attribute navn of J51100 : Label is "PCIeX1-GF-2D-1000-1K-O36";
attribute pakke_opprettet : string;
attribute pakke_opprettet of J51100 : Label is "07.06.2015 17:49:10";
attribute pakke_opprettet_av : string;
attribute pakke_opprettet_av of J51100 : Label is "815";
attribute pakketype : string;
attribute pakketype of J51100 : Label is "6";
attribute pris : string;
attribute pris of J51100 : Label is "0";
attribute symbol_opprettet : string;
attribute symbol_opprettet of J51100 : Label is "06.07.2014 17:26:37";
attribute symbol_opprettet_av : string;
attribute symbol_opprettet_av of J51100 : Label is "815";
Begin
J51100 : PCIeX1MINUSGFMINUS2DMINUS1000MINUS1KMINUSO36 -- ObjectKind=Part|PrimaryId=J51100|SecondaryId=1
Port Map
(
A1 => PowerSignal_VCC_P5V0, -- ObjectKind=Pin|PrimaryId=J51100-A1
A15 => PowerSignal_GND, -- ObjectKind=Pin|PrimaryId=J51100-A15
A16 => PowerSignal_VCC_EXTRA, -- ObjectKind=Pin|PrimaryId=J51100-A16
A17 => PowerSignal_VCC_P5V0, -- ObjectKind=Pin|PrimaryId=J51100-A17
A18 => PowerSignal_VCC_P18V, -- ObjectKind=Pin|PrimaryId=J51100-A18
B1 => NamedSignal_KORT_INNSATT, -- ObjectKind=Pin|PrimaryId=J51100-B1
B2 => NamedSignal_TRIGGER, -- ObjectKind=Pin|PrimaryId=J51100-B2
B3 => NamedSignal_LIMIT, -- ObjectKind=Pin|PrimaryId=J51100-B3
B4 => NamedSignal_INTERRUPT, -- ObjectKind=Pin|PrimaryId=J51100-B4
B5 => NamedSignal_B5, -- ObjectKind=Pin|PrimaryId=J51100-B5
B6 => NamedSignal_B6, -- ObjectKind=Pin|PrimaryId=J51100-B6
B7 => NamedSignal_B7, -- ObjectKind=Pin|PrimaryId=J51100-B7
B8 => NamedSignal_B8, -- ObjectKind=Pin|PrimaryId=J51100-B8
B9 => NamedSignal_B9, -- ObjectKind=Pin|PrimaryId=J51100-B9
B10 => NamedSignal_B10, -- ObjectKind=Pin|PrimaryId=J51100-B10
B11 => NamedSignal_B11, -- ObjectKind=Pin|PrimaryId=J51100-B11
B12 => NamedSignal_B12, -- ObjectKind=Pin|PrimaryId=J51100-B12
B13 => NamedSignal_B13, -- ObjectKind=Pin|PrimaryId=J51100-B13
B14 => NamedSignal_B14, -- ObjectKind=Pin|PrimaryId=J51100-B14
B15 => PowerSignal_GND, -- ObjectKind=Pin|PrimaryId=J51100-B15
B16 => PowerSignal_VCC_EXTRA, -- ObjectKind=Pin|PrimaryId=J51100-B16
B17 => PowerSignal_VCC_P5V0, -- ObjectKind=Pin|PrimaryId=J51100-B17
B18 => PowerSignal_VCC_P18V -- ObjectKind=Pin|PrimaryId=J51100-B18
);
-- Signal Assignments
---------------------
PowerSignal_GND <= '0'; -- ObjectKind=Net|PrimaryId=GND
End Structure;
------------------------------------------------------------
------------------------------------------------------------
-- VHDL TK512_Optisk_Mottaker
-- 2014 7 12 23 24 4
-- 2015 7 5 14 55 23
-- Created By "DXP VHDL Generator"
-- "Copyright (c) 2002-2014 Altium Limited"
-- Product Version: 14.3.11.33708
-- Product Version: 15.0.7.36915
------------------------------------------------------------
------------------------------------------------------------
......@@ -34,6 +34,14 @@ Architecture Structure Of TK512_Optisk_Mottaker Is
);
End Component;
Component X_47R -- ObjectKind=Part|PrimaryId=R51205|SecondaryId=1
port
(
X_1 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=R51205-1
X_2 : inout STD_LOGIC -- ObjectKind=Pin|PrimaryId=R51205-2
);
End Component;
Component X_74HC14 -- ObjectKind=Part|PrimaryId=U51201|SecondaryId=1
port
(
......@@ -99,24 +107,38 @@ Architecture Structure Of TK512_Optisk_Mottaker Is
);
End Component;
Component SMD_LED_Red -- ObjectKind=Part|PrimaryId=D51201|SecondaryId=1
port
(
X_1 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=D51201-1
X_2 : inout STD_LOGIC -- ObjectKind=Pin|PrimaryId=D51201-2
);
End Component;
Signal PinSignal_C51200_2 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetC51200_2
Signal PinSignal_C51201_1 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetC51201_1
Signal PinSignal_C51201_2 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetC51201_2
Signal PinSignal_C51203_2 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetC51203_2
Signal PinSignal_D51200_K : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetD51200_K
Signal PinSignal_D51201_2 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetD51201_2
Signal PinSignal_J51200_1 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetJ51200_1
Signal PinSignal_J51202_1 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetJ51202_1
Signal PinSignal_L51200_1 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetL51200_1
Signal PinSignal_R51205_1 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetR51205_1
Signal PinSignal_U51200_3 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU51200_3
Signal PinSignal_U51201_11 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU51201_11
Signal PinSignal_U51201_2 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU51201_2
Signal PinSignal_U51201_6 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU51201_6
Signal PowerSignal_GND : STD_LOGIC; -- ObjectKind=Net|PrimaryId=GND
Signal PowerSignal_PLUS5 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=+5
Signal PowerSignal_VCC_P5V0 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=VCC_P5V0
attribute antall : string;
attribute antall of R51205 : Label is "100";
attribute beskrivelse : string;
attribute beskrivelse of U51200 : Label is "TOSLINK Reciever";
attribute beskrivelse of R51205 : Label is "47R 0.1W 5% Thick film resistor";
attribute beskrivelse of D51201 : Label is "SMD";
attribute CaseMINUSEIA : string;
attribute CaseMINUSEIA of R51204 : Label is "0805";
......@@ -143,7 +165,27 @@ Architecture Structure Of TK512_Optisk_Mottaker Is
attribute CaseMINUSMetric of C51200 : Label is "3216";
attribute Database_Table_Name : string;
attribute Database_Table_Name of U51201 : Label is "altium";
attribute Database_Table_Name of U51200 : Label is "altium";
attribute Database_Table_Name of R51205 : Label is "altium";
attribute Database_Table_Name of J51203 : Label is "altium";
attribute Database_Table_Name of J51202 : Label is "altium";
attribute Database_Table_Name of J51201 : Label is "altium";
attribute Database_Table_Name of J51200 : Label is "altium";
attribute Database_Table_Name of D51201 : Label is "altium";
attribute Database_Table_Name of D51200 : Label is "altium";
attribute dybde : string;
attribute dybde of R51205 : Label is "1";
attribute hylle : string;
attribute hylle of R51205 : Label is "6";
attribute kolonne : string;
attribute kolonne of R51205 : Label is "-1";
attribute lager_type : string;
attribute lager_type of R51205 : Label is "Fremlager";
attribute leverandor : string;
attribute leverandor of U51200 : Label is "Farnell";
......@@ -160,18 +202,28 @@ Architecture Structure Of TK512_Optisk_Mottaker Is
attribute navn : string;
attribute navn of U51200 : Label is "GP1FAV50RK";
attribute navn of R51205 : Label is "47R";
attribute navn of D51201 : Label is "SMD LED Red";
attribute nokkelord : string;
attribute nokkelord of U51200 : Label is "Optic, fibre";
attribute nokkelord of R51205 : Label is "Resistor";
attribute nokkelord of D51201 : Label is "SMD";
attribute pakke_opprettet : string;
attribute pakke_opprettet of U51200 : Label is "28.06.2014 18:02:12";
attribute pakke_opprettet of R51205 : Label is "08.07.2014 21:15:30";
attribute pakke_opprettet of D51201 : Label is "06.07.2014 18:55:44";
attribute pakke_opprettet_av : string;
attribute pakke_opprettet_av of U51200 : Label is "815";
attribute pakke_opprettet_av of R51205 : Label is "815";
attribute pakke_opprettet_av of D51201 : Label is "815";
attribute pakketype : string;
attribute pakketype of U51200 : Label is "92";
attribute pakketype of R51205 : Label is "93";
attribute pakketype of D51201 : Label is "93";
attribute Power : string;
attribute Power of R51204 : Label is "0.125 W";
......@@ -182,10 +234,15 @@ Architecture Structure Of TK512_Optisk_Mottaker Is
attribute pris : string;
attribute pris of U51200 : Label is "12";
attribute pris of R51205 : Label is "0";
attribute pris of D51201 : Label is "1";
attribute produsent : string;
attribute produsent of U51200 : Label is "Sharp";
attribute rad : string;
attribute rad of R51205 : Label is "-1";
attribute Rated_Voltage : string;
attribute Rated_Voltage of C51205 : Label is "25 V";
attribute Rated_Voltage of C51203 : Label is "25 V";
......@@ -193,11 +250,18 @@ Architecture Structure Of TK512_Optisk_Mottaker Is
attribute Rated_Voltage of C51201 : Label is "25 V";
attribute Rated_Voltage of C51200 : Label is "25 V";
attribute rom : string;
attribute rom of R51205 : Label is "OV";
attribute symbol_opprettet : string;
attribute symbol_opprettet of U51200 : Label is "28.06.2014 15:42:01";
attribute symbol_opprettet of R51205 : Label is "08.07.2014 21:16:33";
attribute symbol_opprettet of D51201 : Label is "06.07.2014 18:59:47";
attribute symbol_opprettet_av : string;
attribute symbol_opprettet_av of U51200 : Label is "815";
attribute symbol_opprettet_av of R51205 : Label is "815";
attribute symbol_opprettet_av of D51201 : Label is "815";
attribute Technology : string;
attribute Technology of R51204 : Label is "SMT";
......@@ -242,7 +306,7 @@ Begin
Port Map
(
X_7 => PowerSignal_GND, -- ObjectKind=Pin|PrimaryId=U51201-7
X_14 => PowerSignal_PLUS5 -- ObjectKind=Pin|PrimaryId=U51201-14
X_14 => PowerSignal_VCC_P5V0 -- ObjectKind=Pin|PrimaryId=U51201-14
);
U51201 : X_74HC14 -- ObjectKind=Part|PrimaryId=U51201|SecondaryId=6
......@@ -263,14 +327,14 @@ Begin
Port Map
(
X_8 => PinSignal_J51202_1, -- ObjectKind=Pin|PrimaryId=U51201-8
X_9 => PinSignal_U51201_6 -- ObjectKind=Pin|PrimaryId=U51201-9
X_9 => PinSignal_R51205_1 -- ObjectKind=Pin|PrimaryId=U51201-9
);
U51201 : X_74HC14 -- ObjectKind=Part|PrimaryId=U51201|SecondaryId=3
Port Map
(
X_5 => PinSignal_C51203_2, -- ObjectKind=Pin|PrimaryId=U51201-5
X_6 => PinSignal_U51201_6 -- ObjectKind=Pin|PrimaryId=U51201-6
X_6 => PinSignal_R51205_1 -- ObjectKind=Pin|PrimaryId=U51201-6
);
U51201 : X_74HC14 -- ObjectKind=Part|PrimaryId=U51201|SecondaryId=2
......@@ -290,11 +354,18 @@ Begin
U51200 : GP1FAV50RK -- ObjectKind=Part|PrimaryId=U51200|SecondaryId=1
Port Map
(
X_1 => PowerSignal_PLUS5, -- ObjectKind=Pin|PrimaryId=U51200-1
X_1 => PowerSignal_VCC_P5V0, -- ObjectKind=Pin|PrimaryId=U51200-1
X_2 => PowerSignal_GND, -- ObjectKind=Pin|PrimaryId=U51200-2
X_3 => PinSignal_U51200_3 -- ObjectKind=Pin|PrimaryId=U51200-3
);
R51205 : X_47R -- ObjectKind=Part|PrimaryId=R51205|SecondaryId=1
Port Map
(
X_1 => PinSignal_R51205_1, -- ObjectKind=Pin|PrimaryId=R51205-1
X_2 => PinSignal_D51201_2 -- ObjectKind=Pin|PrimaryId=R51205-2
);
R51204 : CMPMINUS1013MINUS00062MINUS1 -- ObjectKind=Part|PrimaryId=R51204|SecondaryId=1
Port Map
(
......@@ -340,7 +411,7 @@ Begin
J51203 : JST_2pin -- ObjectKind=Part|PrimaryId=J51203|SecondaryId=1
Port Map
(
X_1 => PowerSignal_PLUS5, -- ObjectKind=Pin|PrimaryId=J51203-1
X_1 => PowerSignal_VCC_P5V0, -- ObjectKind=Pin|PrimaryId=J51203-1
X_2 => PowerSignal_GND -- ObjectKind=Pin|PrimaryId=J51203-2
);
......@@ -365,6 +436,13 @@ Begin
X_2 => PowerSignal_GND -- ObjectKind=Pin|PrimaryId=J51200-2
);
D51201 : SMD_LED_Red -- ObjectKind=Part|PrimaryId=D51201|SecondaryId=1
Port Map
(
X_1 => PowerSignal_VCC_P5V0, -- ObjectKind=Pin|PrimaryId=D51201-1
X_2 => PinSignal_D51201_2 -- ObjectKind=Pin|PrimaryId=D51201-2
);
D51200 : X_1N4148 -- ObjectKind=Part|PrimaryId=D51200|SecondaryId=1
Port Map
(
......@@ -376,14 +454,14 @@ Begin
Port Map
(
X_1 => PowerSignal_GND, -- ObjectKind=Pin|PrimaryId=C51205-1
X_2 => PowerSignal_PLUS5 -- ObjectKind=Pin|PrimaryId=C51205-2
X_2 => PowerSignal_VCC_P5V0 -- ObjectKind=Pin|PrimaryId=C51205-2
);
C51204 : CAP -- ObjectKind=Part|PrimaryId=C51204|SecondaryId=1
Port Map
(
X_1 => PowerSignal_GND, -- ObjectKind=Pin|PrimaryId=C51204-1
X_2 => PowerSignal_PLUS5 -- ObjectKind=Pin|PrimaryId=C51204-2
X_2 => PowerSignal_VCC_P5V0 -- ObjectKind=Pin|PrimaryId=C51204-2
);
C51203 : CMPMINUS1036MINUS04408MINUS1 -- ObjectKind=Part|PrimaryId=C51203|SecondaryId=1
......
------------------------------------------------------------
-- VHDL TK513_Limiter
-- 2014 7 12 23 24 4
-- 2015 7 5 14 55 24
-- Created By "DXP VHDL Generator"
-- "Copyright (c) 2002-2014 Altium Limited"
-- Product Version: 14.3.11.33708
-- Product Version: 15.0.7.36915
------------------------------------------------------------
------------------------------------------------------------
......@@ -136,7 +136,6 @@ Architecture Structure Of TK513_Limiter Is
Signal NamedSignal_LED : STD_LOGIC; -- ObjectKind=Net|PrimaryId=LED
Signal NamedSignal_LIMITER_OUT : STD_LOGIC; -- ObjectKind=Net|PrimaryId=LIMITER_OUT
Signal NamedSignal_POT : STD_LOGIC; -- ObjectKind=Net|PrimaryId=POT
Signal PinSignal_C51301_1 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetC51301_1
Signal PinSignal_D51300_A : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetD51300_A
Signal PinSignal_D51301_A : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetD51301_A
Signal PinSignal_J51302_1 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetJ51302_1
......@@ -378,7 +377,7 @@ Begin
Port Map
(
X_1 => NamedSignal_DC_IN, -- ObjectKind=Pin|PrimaryId=R51301-1
X_2 => PinSignal_C51301_1 -- ObjectKind=Pin|PrimaryId=R51301-2
X_2 => PowerSignal_GND -- ObjectKind=Pin|PrimaryId=R51301-2
);
R51300 : CMPMINUS1013MINUS00062MINUS1 -- ObjectKind=Part|PrimaryId=R51300|SecondaryId=1
......@@ -434,14 +433,14 @@ Begin
D51303 : X_1N5819 -- ObjectKind=Part|PrimaryId=D51303|SecondaryId=1
Port Map
(
A => PinSignal_C51301_1, -- ObjectKind=Pin|PrimaryId=D51303-A
A => PowerSignal_GND, -- ObjectKind=Pin|PrimaryId=D51303-A
K => PinSignal_D51301_A -- ObjectKind=Pin|PrimaryId=D51303-K
);
D51302 : X_1N5819 -- ObjectKind=Part|PrimaryId=D51302|SecondaryId=1
Port Map
(
A => PinSignal_C51301_1, -- ObjectKind=Pin|PrimaryId=D51302-A
A => PowerSignal_GND, -- ObjectKind=Pin|PrimaryId=D51302-A
K => PinSignal_D51300_A -- ObjectKind=Pin|PrimaryId=D51302-K
);
......@@ -490,7 +489,7 @@ Begin
C51301 : CMPMINUS1036MINUS04418MINUS1 -- ObjectKind=Part|PrimaryId=C51301|SecondaryId=1
Port Map
(
X_1 => PinSignal_C51301_1, -- ObjectKind=Pin|PrimaryId=C51301-1
X_1 => PowerSignal_GND, -- ObjectKind=Pin|PrimaryId=C51301-1
X_2 => NamedSignal_DC_IN -- ObjectKind=Pin|PrimaryId=C51301-2
);
......
------------------------------------------------------------
-- VHDL TK516_EKSTRAMINUSPSU
-- 2014 7 12 23 24 5
-- 2015 7 5 14 55 24
-- Created By "DXP VHDL Generator"
-- "Copyright (c) 2002-2014 Altium Limited"
-- Product Version: 14.3.11.33708
-- Product Version: 15.0.7.36915
------------------------------------------------------------
------------------------------------------------------------
......
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-- VHDL TK517_P5V0MINUSPSU
-- 2014 7 12 23 24 5
-- 2015 7 5 14 55 24
-- Created By "DXP VHDL Generator"
-- "Copyright (c) 2002-2014 Altium Limited"
-- Product Version: 14.3.11.33708
-- Product Version: 15.0.7.36915
------------------------------------------------------------
------------------------------------------------------------
......
------------------------------------------------------------
-- VHDL TK518_P18VMINUSPSU
-- 2014 7 12 23 24 5
-- 2015 7 5 14 55 24
-- Created By "DXP VHDL Generator"
-- "Copyright (c) 2002-2014 Altium Limited"
-- Product Version: 14.3.11.33708
-- Product Version: 15.0.7.36915
------------------------------------------------------------
------------------------------------------------------------
......
------------------------------------------------------------
-- VHDL TK519_Spenningsvakt
-- 2014 7 12 23 24 5
-- 2015 7 5 14 55 24
-- Created By "DXP VHDL Generator"
-- "Copyright (c) 2002-2014 Altium Limited"
-- Product Version: 14.3.11.33708
-- Product Version: 15.0.7.36915