Commit 2c597046 authored by Øystein Smith's avatar Øystein Smith
Browse files

Omstrukturert (igjen) tror jeg begynner å bli fornøyd

parent 719ca7c8
------------------------------------------------------------
-- VHDL TK511_Blindkort
-- 2014 7 6 17 49 12
-- 2014 7 8 19 13 37
-- Created By "DXP VHDL Generator"
-- "Copyright (c) 2002-2014 Altium Limited"
-- Product Version: 14.3.11.33708
-- Product Version: 14.3.10.33625
------------------------------------------------------------
------------------------------------------------------------
......@@ -14,6 +14,37 @@ Library IEEE;
Use IEEE.std_logic_1164.all;
Entity TK511_Blindkort Is
port
(
A1 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=A1
A2 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=A2
A3 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=A3
A4 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=A4
A5 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=A5
A6 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=A6
A7 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=A7
A8 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=A8
A9 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=A9
B3 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=B3
B4 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=B4
B5 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=B5
B6 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=B6
B7 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=B7
B8 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=B8
B9 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=B9
B10 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=B10
B11 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=B11
B12 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=B12
B13 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=B13
B14 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=B14
FEIL : Out STD_LOGIC; -- ObjectKind=Port|PrimaryId=FEIL
INTERRUPT : Out STD_LOGIC; -- ObjectKind=Port|PrimaryId=INTERRUPT
KORT_INNSATT : Out STD_LOGIC; -- ObjectKind=Port|PrimaryId=KORT INNSATT
LIMIT : In STD_LOGIC; -- ObjectKind=Port|PrimaryId=LIMIT
RESERVELED : Out STD_LOGIC; -- ObjectKind=Port|PrimaryId=RESERVELED
STATUS : Out STD_LOGIC; -- ObjectKind=Port|PrimaryId=STATUS
TRIGGER : In STD_LOGIC -- ObjectKind=Port|PrimaryId=TRIGGER
);
attribute MacroCell : boolean;
End TK511_Blindkort;
......
------------------------------------------------------------
-- VHDL TK516_EKSTRAMINUSPSU
-- 2014 7 8 19 13 37
-- Created By "DXP VHDL Generator"
-- "Copyright (c) 2002-2014 Altium Limited"
-- Product Version: 14.3.10.33625
------------------------------------------------------------
------------------------------------------------------------
-- VHDL TK516_EKSTRAMINUSPSU
------------------------------------------------------------
Library IEEE;
Use IEEE.std_logic_1164.all;
Entity TK516_EKSTRAMINUSPSU Is
attribute MacroCell : boolean;
End TK516_EKSTRAMINUSPSU;
------------------------------------------------------------
------------------------------------------------------------
Architecture Structure Of TK516_EKSTRAMINUSPSU Is
Begin
End Structure;
------------------------------------------------------------
------------------------------------------------------------
-- VHDL TK517_P5V0MINUSPSU
-- 2014 7 6 17 49 12
-- 2014 7 8 19 13 37
-- Created By "DXP VHDL Generator"
-- "Copyright (c) 2002-2014 Altium Limited"
-- Product Version: 14.3.11.33708
-- Product Version: 14.3.10.33625
------------------------------------------------------------
------------------------------------------------------------
......
------------------------------------------------------------
-- VHDL TK518_P18VMINUSPSU
-- 2014 7 6 17 49 12
-- 2014 7 8 19 13 37
-- Created By "DXP VHDL Generator"
-- "Copyright (c) 2002-2014 Altium Limited"
-- Product Version: 14.3.11.33708
-- Product Version: 14.3.10.33625
------------------------------------------------------------
------------------------------------------------------------
......
------------------------------------------------------------
-- VHDL TK519_Spenningsvakt
-- 2014 7 6 17 49 12
-- 2014 7 8 19 13 37
-- Created By "DXP VHDL Generator"
-- "Copyright (c) 2002-2014 Altium Limited"
-- Product Version: 14.3.11.33708
-- Product Version: 14.3.10.33625
------------------------------------------------------------
------------------------------------------------------------
......@@ -14,6 +14,37 @@ Library IEEE;
Use IEEE.std_logic_1164.all;
Entity TK519_Spenningsvakt Is
port
(
A1 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=A1
A2 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=A2
A3 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=A3
A4 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=A4
A5 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=A5
A6 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=A6
A7 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=A7
A8 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=A8
A9 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=A9
B3 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=B3
B4 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=B4
B5 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=B5
B6 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=B6
B7 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=B7
B8 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=B8
B9 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=B9
B10 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=B10
B11 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=B11
B12 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=B12
B13 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=B13
B14 : InOut STD_LOGIC; -- ObjectKind=Port|PrimaryId=B14
FEIL : Out STD_LOGIC; -- ObjectKind=Port|PrimaryId=FEIL
INTERRUPT : Out STD_LOGIC; -- ObjectKind=Port|PrimaryId=INTERRUPT
KORT_INNSATT : Out STD_LOGIC; -- ObjectKind=Port|PrimaryId=KORT INNSATT
LIMIT : In STD_LOGIC; -- ObjectKind=Port|PrimaryId=LIMIT
RESERVELED : Out STD_LOGIC; -- ObjectKind=Port|PrimaryId=RESERVELED
STATUS : Out STD_LOGIC; -- ObjectKind=Port|PrimaryId=STATUS
TRIGGER : In STD_LOGIC -- ObjectKind=Port|PrimaryId=TRIGGER
);
attribute MacroCell : boolean;
End TK519_Spenningsvakt;
......
------------------------------------------------------------
-- VHDL TK520_GDTMINUSTrafo
-- 2014 7 6 17 49 12
-- 2014 7 8 19 13 37
-- Created By "DXP VHDL Generator"
-- "Copyright (c) 2002-2014 Altium Limited"
-- Product Version: 14.3.11.33708
-- Product Version: 14.3.10.33625
------------------------------------------------------------
------------------------------------------------------------
......@@ -34,112 +34,112 @@ End TK520_GDTMINUSTrafo;
------------------------------------------------------------
Architecture Structure Of TK520_GDTMINUSTrafo Is
Component GDT_1_1_1 -- ObjectKind=Part|PrimaryId=T1|SecondaryId=1
Component GDT_1_1_1 -- ObjectKind=Part|PrimaryId=T52000|SecondaryId=1
port
(
X_1 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=T1-1
X_5 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=T1-5
X_6 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=T1-6
X_7 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=T1-7
X_9 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=T1-9
X_10 : inout STD_LOGIC -- ObjectKind=Pin|PrimaryId=T1-10
X_1 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=T52000-1
X_5 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=T52000-5
X_6 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=T52000-6
X_7 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=T52000-7
X_9 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=T52000-9
X_10 : inout STD_LOGIC -- ObjectKind=Pin|PrimaryId=T52000-10
);
End Component;
Component JST_2pin -- ObjectKind=Part|PrimaryId=J1|SecondaryId=1
Component JST_2pin -- ObjectKind=Part|PrimaryId=J52001|SecondaryId=1
port
(
X_1 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=J1-1
X_2 : inout STD_LOGIC -- ObjectKind=Pin|PrimaryId=J1-2
X_1 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=J52001-1
X_2 : inout STD_LOGIC -- ObjectKind=Pin|PrimaryId=J52001-2
);
End Component;
Component JST_4pin -- ObjectKind=Part|PrimaryId=J2|SecondaryId=1
Component JST_4pin -- ObjectKind=Part|PrimaryId=J52000|SecondaryId=1
port
(
X_1 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=J2-1
X_2 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=J2-2
X_3 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=J2-3
X_4 : inout STD_LOGIC -- ObjectKind=Pin|PrimaryId=J2-4
X_1 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=J52000-1
X_2 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=J52000-2
X_3 : inout STD_LOGIC; -- ObjectKind=Pin|PrimaryId=J52000-3
X_4 : inout STD_LOGIC -- ObjectKind=Pin|PrimaryId=J52000-4
);
End Component;
Signal PinSignal_J2_1 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetJ2_1
Signal PinSignal_J2_2 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetJ2_2
Signal PinSignal_J2_3 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetJ2_3
Signal PinSignal_J2_4 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetJ2_4
Signal PinSignal_J3_1 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetJ3_1
Signal PinSignal_J3_2 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetJ3_2
Signal PinSignal_J3_3 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetJ3_3
Signal PinSignal_J3_4 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetJ3_4
Signal PinSignal_J52000_1 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetJ52000_1
Signal PinSignal_J52000_2 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetJ52000_2
Signal PinSignal_J52000_3 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetJ52000_3
Signal PinSignal_J52000_4 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetJ52000_4
Signal PinSignal_J52002_1 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetJ52002_1
Signal PinSignal_J52002_2 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetJ52002_2
Signal PinSignal_J52002_3 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetJ52002_3
Signal PinSignal_J52002_4 : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetJ52002_4
Begin
T2 : GDT_1_1_1 -- ObjectKind=Part|PrimaryId=T2|SecondaryId=1
T52001 : GDT_1_1_1 -- ObjectKind=Part|PrimaryId=T52001|SecondaryId=1
Port Map
(
X_1 => GDT2_IN, -- ObjectKind=Pin|PrimaryId=T2-1
X_5 => GDT1_IN, -- ObjectKind=Pin|PrimaryId=T2-5
X_6 => PinSignal_J3_1, -- ObjectKind=Pin|PrimaryId=T2-6
X_7 => PinSignal_J3_2, -- ObjectKind=Pin|PrimaryId=T2-7
X_9 => PinSignal_J3_3, -- ObjectKind=Pin|PrimaryId=T2-9
X_10 => PinSignal_J3_4 -- ObjectKind=Pin|PrimaryId=T2-10
X_1 => GDT2_IN, -- ObjectKind=Pin|PrimaryId=T52001-1
X_5 => GDT1_IN, -- ObjectKind=Pin|PrimaryId=T52001-5
X_6 => PinSignal_J52002_1, -- ObjectKind=Pin|PrimaryId=T52001-6
X_7 => PinSignal_J52002_2, -- ObjectKind=Pin|PrimaryId=T52001-7
X_9 => PinSignal_J52002_3, -- ObjectKind=Pin|PrimaryId=T52001-9
X_10 => PinSignal_J52002_4 -- ObjectKind=Pin|PrimaryId=T52001-10
);
T1 : GDT_1_1_1 -- ObjectKind=Part|PrimaryId=T1|SecondaryId=1
T52000 : GDT_1_1_1 -- ObjectKind=Part|PrimaryId=T52000|SecondaryId=1
Port Map
(
X_1 => GDT1_IN, -- ObjectKind=Pin|PrimaryId=T1-1
X_5 => GDT2_IN, -- ObjectKind=Pin|PrimaryId=T1-5
X_6 => PinSignal_J2_1, -- ObjectKind=Pin|PrimaryId=T1-6
X_7 => PinSignal_J2_2, -- ObjectKind=Pin|PrimaryId=T1-7
X_9 => PinSignal_J2_3, -- ObjectKind=Pin|PrimaryId=T1-9
X_10 => PinSignal_J2_4 -- ObjectKind=Pin|PrimaryId=T1-10
X_1 => GDT1_IN, -- ObjectKind=Pin|PrimaryId=T52000-1
X_5 => GDT2_IN, -- ObjectKind=Pin|PrimaryId=T52000-5
X_6 => PinSignal_J52000_1, -- ObjectKind=Pin|PrimaryId=T52000-6
X_7 => PinSignal_J52000_2, -- ObjectKind=Pin|PrimaryId=T52000-7
X_9 => PinSignal_J52000_3, -- ObjectKind=Pin|PrimaryId=T52000-9
X_10 => PinSignal_J52000_4 -- ObjectKind=Pin|PrimaryId=T52000-10
);
J3 : JST_4pin -- ObjectKind=Part|PrimaryId=J3|SecondaryId=1
J52002 : JST_4pin -- ObjectKind=Part|PrimaryId=J52002|SecondaryId=1
Port Map
(
X_1 => PinSignal_J3_1, -- ObjectKind=Pin|PrimaryId=J3-1
X_2 => PinSignal_J3_2, -- ObjectKind=Pin|PrimaryId=J3-2
X_3 => PinSignal_J3_3, -- ObjectKind=Pin|PrimaryId=J3-3
X_4 => PinSignal_J3_4 -- ObjectKind=Pin|PrimaryId=J3-4
X_1 => PinSignal_J52002_1, -- ObjectKind=Pin|PrimaryId=J52002-1
X_2 => PinSignal_J52002_2, -- ObjectKind=Pin|PrimaryId=J52002-2
X_3 => PinSignal_J52002_3, -- ObjectKind=Pin|PrimaryId=J52002-3
X_4 => PinSignal_J52002_4 -- ObjectKind=Pin|PrimaryId=J52002-4
);
J2 : JST_4pin -- ObjectKind=Part|PrimaryId=J2|SecondaryId=1
J52001 : JST_2pin -- ObjectKind=Part|PrimaryId=J52001|SecondaryId=1
Port Map
(
X_1 => PinSignal_J2_1, -- ObjectKind=Pin|PrimaryId=J2-1
X_2 => PinSignal_J2_2, -- ObjectKind=Pin|PrimaryId=J2-2
X_3 => PinSignal_J2_3, -- ObjectKind=Pin|PrimaryId=J2-3
X_4 => PinSignal_J2_4 -- ObjectKind=Pin|PrimaryId=J2-4
X_1 => GDT1_IN, -- ObjectKind=Pin|PrimaryId=J52001-1
X_2 => GDT2_IN -- ObjectKind=Pin|PrimaryId=J52001-2
);
J1 : JST_2pin -- ObjectKind=Part|PrimaryId=J1|SecondaryId=1
J52000 : JST_4pin -- ObjectKind=Part|PrimaryId=J52000|SecondaryId=1
Port Map
(
X_1 => GDT1_IN, -- ObjectKind=Pin|PrimaryId=J1-1
X_2 => GDT2_IN -- ObjectKind=Pin|PrimaryId=J1-2
X_1 => PinSignal_J52000_1, -- ObjectKind=Pin|PrimaryId=J52000-1
X_2 => PinSignal_J52000_2, -- ObjectKind=Pin|PrimaryId=J52000-2
X_3 => PinSignal_J52000_3, -- ObjectKind=Pin|PrimaryId=J52000-3
X_4 => PinSignal_J52000_4 -- ObjectKind=Pin|PrimaryId=J52000-4
);
-- Signal Assignments
---------------------
GDT1_1 <= PinSignal_J2_1; -- ObjectKind=Net|PrimaryId=NetJ2_1
GDT1_2 <= PinSignal_J3_1; -- ObjectKind=Net|PrimaryId=NetJ3_1
GDT2_1 <= PinSignal_J2_2; -- ObjectKind=Net|PrimaryId=NetJ2_2
GDT2_2 <= PinSignal_J3_2; -- ObjectKind=Net|PrimaryId=NetJ3_2
GDT3_1 <= PinSignal_J2_3; -- ObjectKind=Net|PrimaryId=NetJ2_3
GDT3_2 <= PinSignal_J3_3; -- ObjectKind=Net|PrimaryId=NetJ3_3
GDT4_1 <= PinSignal_J2_4; -- ObjectKind=Net|PrimaryId=NetJ2_4
GDT4_2 <= PinSignal_J3_4; -- ObjectKind=Net|PrimaryId=NetJ3_4
PinSignal_J2_1 <= GDT1_1; -- ObjectKind=Net|PrimaryId=NetJ2_1
PinSignal_J2_2 <= GDT2_1; -- ObjectKind=Net|PrimaryId=NetJ2_2
PinSignal_J2_3 <= GDT3_1; -- ObjectKind=Net|PrimaryId=NetJ2_3
PinSignal_J2_4 <= GDT4_1; -- ObjectKind=Net|PrimaryId=NetJ2_4
PinSignal_J3_1 <= GDT1_2; -- ObjectKind=Net|PrimaryId=NetJ3_1
PinSignal_J3_2 <= GDT2_2; -- ObjectKind=Net|PrimaryId=NetJ3_2
PinSignal_J3_3 <= GDT3_2; -- ObjectKind=Net|PrimaryId=NetJ3_3
PinSignal_J3_4 <= GDT4_2; -- ObjectKind=Net|PrimaryId=NetJ3_4
GDT1_1 <= PinSignal_J52000_1; -- ObjectKind=Net|PrimaryId=NetJ52000_1
GDT1_2 <= PinSignal_J52002_1; -- ObjectKind=Net|PrimaryId=NetJ52002_1
GDT2_1 <= PinSignal_J52000_2; -- ObjectKind=Net|PrimaryId=NetJ52000_2
GDT2_2 <= PinSignal_J52002_2; -- ObjectKind=Net|PrimaryId=NetJ52002_2
GDT3_1 <= PinSignal_J52000_3; -- ObjectKind=Net|PrimaryId=NetJ52000_3
GDT3_2 <= PinSignal_J52002_3; -- ObjectKind=Net|PrimaryId=NetJ52002_3
GDT4_1 <= PinSignal_J52000_4; -- ObjectKind=Net|PrimaryId=NetJ52000_4
GDT4_2 <= PinSignal_J52002_4; -- ObjectKind=Net|PrimaryId=NetJ52002_4
PinSignal_J52000_1 <= GDT1_1; -- ObjectKind=Net|PrimaryId=NetJ52000_1
PinSignal_J52000_2 <= GDT2_1; -- ObjectKind=Net|PrimaryId=NetJ52000_2
PinSignal_J52000_3 <= GDT3_1; -- ObjectKind=Net|PrimaryId=NetJ52000_3
PinSignal_J52000_4 <= GDT4_1; -- ObjectKind=Net|PrimaryId=NetJ52000_4
PinSignal_J52002_1 <= GDT1_2; -- ObjectKind=Net|PrimaryId=NetJ52002_1
PinSignal_J52002_2 <= GDT2_2; -- ObjectKind=Net|PrimaryId=NetJ52002_2
PinSignal_J52002_3 <= GDT3_2; -- ObjectKind=Net|PrimaryId=NetJ52002_3
PinSignal_J52002_4 <= GDT4_2; -- ObjectKind=Net|PrimaryId=NetJ52002_4
End Structure;
------------------------------------------------------------
......
------------------------------------------------------------
-- VHDL TK525_Kraftforsyning
-- 2014 7 6 17 49 11
-- 2014 7 8 19 13 36
-- Created By "DXP VHDL Generator"
-- "Copyright (c) 2002-2014 Altium Limited"
-- Product Version: 14.3.11.33708
-- Product Version: 14.3.10.33625
------------------------------------------------------------
------------------------------------------------------------
......
------------------------------------------------------------
-- VHDL TK530_Kraftbakplan
-- 2014 7 6 17 49 11
-- 2014 7 8 19 13 36
-- Created By "DXP VHDL Generator"
-- "Copyright (c) 2002-2014 Altium Limited"
-- Product Version: 14.3.11.33708
-- Product Version: 14.3.10.33625
------------------------------------------------------------
------------------------------------------------------------
......@@ -25,8 +25,6 @@ Entity TK530_Kraftbakplan Is
GDT4_1 : In STD_LOGIC; -- ObjectKind=Port|PrimaryId=GDT4_1
GDT4_2 : In STD_LOGIC; -- ObjectKind=Port|PrimaryId=GDT4_2
GND_HV : In STD_LOGIC; -- ObjectKind=Port|PrimaryId=GND_HV
OUTA : Out STD_LOGIC; -- ObjectKind=Port|PrimaryId=OUTA
OUTB : Out STD_LOGIC; -- ObjectKind=Port|PrimaryId=OUTB
VCC_P18V0 : In STD_LOGIC -- ObjectKind=Port|PrimaryId=VCC_P18V0
);
attribute MacroCell : boolean;
......@@ -36,57 +34,9 @@ End TK530_Kraftbakplan;
------------------------------------------------------------
Architecture Structure Of TK530_Kraftbakplan Is
Component TK531_Utgangstrinn -- ObjectKind=Sheet Symbol|PrimaryId=TK531_1
port
(
GDT1 : in STD_LOGIC; -- ObjectKind=Sheet Entry|PrimaryId=TK531_Utgangstrinn.SchDoc-GDT1
GDT2 : in STD_LOGIC; -- ObjectKind=Sheet Entry|PrimaryId=TK531_Utgangstrinn.SchDoc-GDT2
GDT3 : in STD_LOGIC; -- ObjectKind=Sheet Entry|PrimaryId=TK531_Utgangstrinn.SchDoc-GDT3
GDT4 : in STD_LOGIC; -- ObjectKind=Sheet Entry|PrimaryId=TK531_Utgangstrinn.SchDoc-GDT4
GND_HV : inout STD_LOGIC; -- ObjectKind=Sheet Entry|PrimaryId=TK531_Utgangstrinn.SchDoc-GND_HV
OUT : out STD_LOGIC; -- ObjectKind=Sheet Entry|PrimaryId=TK531_Utgangstrinn.SchDoc-OUT
VCC_P18V0 : inout STD_LOGIC -- ObjectKind=Sheet Entry|PrimaryId=TK531_Utgangstrinn.SchDoc-VCC_P18V0
);
End Component;
Component TK532_Utgangskondensator -- ObjectKind=Sheet Symbol|PrimaryId=TK532
port
(
IN : in STD_LOGIC; -- ObjectKind=Sheet Entry|PrimaryId=TK532_Utgangskondensator.SchDoc-IN
OUT : out STD_LOGIC -- ObjectKind=Sheet Entry|PrimaryId=TK532_Utgangskondensator.SchDoc-OUT
);
End Component;
Signal PinSignal_TK531_1_OUT : STD_LOGIC; -- ObjectKind=Net|PrimaryId=OUT
Signal PinSignal_TK531_2_OUT : STD_LOGIC; -- ObjectKind=Net|PrimaryId=OUT
Signal PinSignal_TK532_OUT : STD_LOGIC; -- ObjectKind=Net|PrimaryId=OUT
Begin
TK532 : TK532_Utgangskondensator -- ObjectKind=Sheet Symbol|PrimaryId=TK532
Port Map
(
IN => PinSignal_TK531_2_OUT, -- ObjectKind=Sheet Entry|PrimaryId=TK532_Utgangskondensator.SchDoc-IN
OUT => PinSignal_TK532_OUT -- ObjectKind=Sheet Entry|PrimaryId=TK532_Utgangskondensator.SchDoc-OUT
);
TK531_2 : TK531_Utgangstrinn -- ObjectKind=Sheet Symbol|PrimaryId=TK531_2
Port Map
(
OUT => PinSignal_TK531_2_OUT -- ObjectKind=Sheet Entry|PrimaryId=TK531_Utgangstrinn.SchDoc-OUT
);
TK531_1 : TK531_Utgangstrinn -- ObjectKind=Sheet Symbol|PrimaryId=TK531_1
Port Map
(
OUT => PinSignal_TK531_1_OUT -- ObjectKind=Sheet Entry|PrimaryId=TK531_Utgangstrinn.SchDoc-OUT
);
-- Signal Assignments
---------------------
OUTA <= PinSignal_TK531_1_OUT; -- ObjectKind=Net|PrimaryId=OUT
OUTB <= PinSignal_TK532_OUT; -- ObjectKind=Net|PrimaryId=OUT
End Structure;
------------------------------------------------------------
------------------------------------------------------------
-- VHDL TK532_Utgangskondensator
-- 2014 7 6 17 49 11
-- 2014 7 8 19 13 37
-- Created By "DXP VHDL Generator"
-- "Copyright (c) 2002-2014 Altium Limited"
-- Product Version: 14.3.11.33708
-- Product Version: 14.3.10.33625
------------------------------------------------------------
------------------------------------------------------------
......
------------------------------------------------------------
-- VHDL TK540_Frontpanel
-- 2014 7 8 19 13 37
-- Created By "DXP VHDL Generator"
-- "Copyright (c) 2002-2014 Altium Limited"
-- Product Version: 14.3.10.33625
------------------------------------------------------------
------------------------------------------------------------
-- VHDL TK540_Frontpanel
------------------------------------------------------------
Library IEEE;
Use IEEE.std_logic_1164.all;
Entity TK540_Frontpanel Is
attribute MacroCell : boolean;
End TK540_Frontpanel;
------------------------------------------------------------
------------------------------------------------------------
Architecture Structure Of TK540_Frontpanel Is
Begin
End Structure;
------------------------------------------------------------
Record=TopLevelDocument|FileName=TK500_Driver.SchDoc
Record=SheetSymbol|Record=SheetSymbol|SourceDocument=TK530_Kraftbakplan.SchDoc|Designator=TK531_1|SchDesignator=TK531_1|FileName=TK531_Utgangstrinn.SchDoc|SymbolType=Normal|RawFileName=TK531_Utgangstrinn.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|Record=SheetSymbol|SourceDocument=TK530_Kraftbakplan.SchDoc|Designator=TK531_2|SchDesignator=TK531_2|FileName=TK531_Utgangstrinn.SchDoc|SymbolType=Normal|RawFileName=TK531_Utgangstrinn.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|Record=SheetSymbol|SourceDocument=TK530_Kraftbakplan.SchDoc|Designator=TK532|SchDesignator=TK532|FileName=TK532_Utgangskondensator.SchDoc|SymbolType=Normal|RawFileName=TK532_Utgangskondensator.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
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