Commit a3cbc11c authored by Johannes Wågen's avatar Johannes Wågen

Added large buffer bitstream

parent af858852
......@@ -9,73 +9,73 @@
<CompileStatus State="Success">
<CurrentStep>Generate Programming File</CurrentStep>
<ConnectionState>Completed</ConnectionState>
<LocalTime>0:00:04:08.7403042</LocalTime>
<XilinxTime>0:03:11:42.5556061</XilinxTime>
<LocalTime>0:00:04:18.2409450</LocalTime>
<XilinxTime>0:02:17:21.0245934</XilinxTime>
</CompileStatus>
<CompileSteps>
<Step Name="Analyzing Diagrams">
<Status>Done</Status>
<Type>Building</Type>
<Duration>0:00:00:02.8136073</Duration>
<Duration>0:00:00:39.2206816</Duration>
</Step>
<Step Name="Building">
<Status>Done</Status>
<Type>Building</Type>
<Duration>0:00:03:50.1776130</Duration>
<Duration>0:00:03:13.1555939</Duration>
</Step>
<Step Name="Transferring">
<Status>Done</Status>
<Type>XilinxCompile</Type>
<Duration>0:00:00:01.6939376</Duration>
<Duration>0:00:00:11.8142543</Duration>
</Step>
<Step Name="Waiting">
<Status>Done</Status>
<Type>XilinxCompile</Type>
<Duration>0:00:00:14.0551463</Duration>
<Duration>0:00:00:14.0504152</Duration>
</Step>
<Step Name="CoreGenerator">
<Status>Done</Status>
<Type>XilinxCompile</Type>
<Duration>0:00:00:02.2173320</Duration>
<Duration>0:00:00:02.0462555</Duration>
</Step>
<Step Name="Synthesize - Vivado">
<Status>Done</Status>
<Type>XilinxCompile</Type>
<Duration>0:01:25:02.4101357</Duration>
<Duration>0:01:17:33.3598137</Duration>
</Step>
<Step Name="Optimize Logic">
<Status>Done</Status>
<Type>XilinxCompile</Type>
<Duration>0:00:05:27.6292463</Duration>
<Duration>0:00:04:55.8761712</Duration>
</Step>
<Step Name="Place">
<Status>Done</Status>
<Type>XilinxCompile</Type>
<Duration>0:00:20:40.0890553</Duration>
<Duration>0:00:18:54.8883029</Duration>
</Step>
<Step Name="Optimize Timing">
<Status>Done</Status>
<Type>XilinxCompile</Type>
<Duration>0:00:50:49.6884355</Duration>
<Duration>0:00:08:29.5294518</Duration>
</Step>
<Step Name="Route">
<Status>Done</Status>
<Type>XilinxCompile</Type>
<Duration>0:00:20:42.7493606</Duration>
<Duration>0:00:18:22.7068288</Duration>
</Step>
<Step Name="Generate Programming File">
<Status>Done</Status>
<Type>XilinxCompile</Type>
<Duration>0:00:08:57.7720312</Duration>
<Duration>0:00:09:02.6177226</Duration>
</Step>
</CompileSteps>
<ReportList>
<Report Name="Estimated Device Utilization (Synthesize)" Type="Utilization">
<ReportItem>
<Resource>Slice Registers</Resource>
<Used>129670</Used>
<Used>129771</Used>
<Total>508400</Total>
<Percent>25.51</Percent>
<Percent>25.53</Percent>
</ReportItem>
<ReportItem>
<Resource>DSP</Resource>
......@@ -85,13 +85,13 @@
</ReportItem>
<ReportItem>
<Resource>Block RAMs</Resource>
<Used>256</Used>
<Used>312</Used>
<Total>795</Total>
<Percent>32.20</Percent>
<Percent>39.25</Percent>
</ReportItem>
<ReportItem>
<Resource>Slice LUTs</Resource>
<Used>97875</Used>
<Used>97866</Used>
<Total>254200</Total>
<Percent>38.50</Percent>
</ReportItem>
......@@ -99,9 +99,9 @@
<Report Name="Final Device Utilization (Place)" Type="Utilization">
<ReportItem>
<Resource>Slice Registers</Resource>
<Used>124044</Used>
<Used>124121</Used>
<Total>508400</Total>
<Percent>24.40</Percent>
<Percent>24.41</Percent>
</ReportItem>
<ReportItem>
<Resource>DSP</Resource>
......@@ -111,21 +111,21 @@
</ReportItem>
<ReportItem>
<Resource>Block RAMs</Resource>
<Used>232</Used>
<Used>288</Used>
<Total>795</Total>
<Percent>29.18</Percent>
<Percent>36.23</Percent>
</ReportItem>
<ReportItem>
<Resource>Slice LUTs</Resource>
<Used>82958</Used>
<Used>82965</Used>
<Total>254200</Total>
<Percent>32.63</Percent>
<Percent>32.64</Percent>
</ReportItem>
<ReportItem>
<Resource>Total Slices</Resource>
<Used>32677</Used>
<Used>32313</Used>
<Total>63550</Total>
<Percent>51.42</Percent>
<Percent>50.85</Percent>
</ReportItem>
</Report>
</ReportList>
......
<?xml version="1.0" encoding="utf-8"?>
<SourceFile Checksum="5903182ABAFB3D04DEEAB35CD5ACB295" xmlns="http://www.ni.com/PlatformFramework">
<SourceFile Checksum="9D77C6BE0E7B66A3DE333AF59C7E81F0" xmlns="http://www.ni.com/PlatformFramework">
<SourceModelFeatureSet>
<ParsableNamespace AssemblyFileVersion="4.5.2.51305" FeatureSetName="GResources" MinimumParsableVersion="4.5.0.0" MinimumSemanticallyEquivalentVersion="4.5.0.0" Name="http://www.ni.com/GResources/SystemModel" Version="4.5.0.49152" />
<ParsableNamespace AssemblyFileVersion="4.5.2.51305" FeatureSetName="LabVIEW FPGA" MinimumParsableVersion="4.5.0.0" MinimumSemanticallyEquivalentVersion="4.5.0.0" Name="http://www.ni.com/LabVIEW.FPGA/SystemDesigner/SystemModel" Version="4.5.0.49152" />
......@@ -81,11 +81,11 @@
<Symbols p6:Path="[{http://www.ni.com/LabVIEW.FPGA/SystemDesigner/SystemModel}TargetToHostFifo]Fifo/DataPort" p7:Process.DataType="UInt8" xmlns:p7="http://www.ni.com/SystemDesigner/SystemModel" xmlns:p6="http://www.ni.com/Core/Proxy" />
</Instance>
<Instance Id="1078" Source="{http://www.ni.com/LabVIEW.FPGA/SystemDesigner/SystemModel}TargetToHostFifo">
<Symbols p6:Path="[{http://www.ni.com/LabVIEW.FPGA/SystemDesigner/SystemModel}TargetToHostFifo]Fifo" p7:Fifo.Depth="16383" p8:Process.AliasName="RX Channel Estimate All Layers MS 1" p8:Process.AssociatedIdentifier="1084" p8:Process.DataType="UInt8" xmlns:p8="http://www.ni.com/SystemDesigner/SystemModel" xmlns:p7="http://www.ni.com/SystemDesigner/Common/SystemModel" xmlns:p6="http://www.ni.com/Core/Proxy" />
<Symbols p6:Path="[{http://www.ni.com/LabVIEW.FPGA/SystemDesigner/SystemModel}TargetToHostFifo]Fifo" p7:Fifo.Depth="131071" p8:Process.AliasName="RX Channel Estimate All Layers MS 1" p8:Process.AssociatedIdentifier="1084" p8:Process.DataType="UInt8" xmlns:p8="http://www.ni.com/SystemDesigner/SystemModel" xmlns:p7="http://www.ni.com/SystemDesigner/Common/SystemModel" xmlns:p6="http://www.ni.com/Core/Proxy" />
<Symbols p6:Path="[{http://www.ni.com/LabVIEW.FPGA/SystemDesigner/SystemModel}TargetToHostFifo]Fifo/DataPort" p7:Process.DataType="UInt8" xmlns:p7="http://www.ni.com/SystemDesigner/SystemModel" xmlns:p6="http://www.ni.com/Core/Proxy" />
</Instance>
<Instance Id="1071" Source="{http://www.ni.com/LabVIEW.FPGA/SystemDesigner/SystemModel}TargetToHostFifo">
<Symbols p6:Path="[{http://www.ni.com/LabVIEW.FPGA/SystemDesigner/SystemModel}TargetToHostFifo]Fifo" p7:Fifo.Depth="16383" p8:Process.AliasName="RX Channel Estimate All Layers MS 0" p8:Process.AssociatedIdentifier="1077" p8:Process.DataType="UInt8" xmlns:p8="http://www.ni.com/SystemDesigner/SystemModel" xmlns:p7="http://www.ni.com/SystemDesigner/Common/SystemModel" xmlns:p6="http://www.ni.com/Core/Proxy" />
<Symbols p6:Path="[{http://www.ni.com/LabVIEW.FPGA/SystemDesigner/SystemModel}TargetToHostFifo]Fifo" p7:Fifo.Depth="131071" p8:Process.AliasName="RX Channel Estimate All Layers MS 0" p8:Process.AssociatedIdentifier="1077" p8:Process.DataType="UInt8" xmlns:p8="http://www.ni.com/SystemDesigner/SystemModel" xmlns:p7="http://www.ni.com/SystemDesigner/Common/SystemModel" xmlns:p6="http://www.ni.com/Core/Proxy" />
<Symbols p6:Path="[{http://www.ni.com/LabVIEW.FPGA/SystemDesigner/SystemModel}TargetToHostFifo]Fifo/DataPort" p7:Process.DataType="UInt8" xmlns:p7="http://www.ni.com/SystemDesigner/SystemModel" xmlns:p6="http://www.ni.com/Core/Proxy" />
</Instance>
<Instance Id="1186" Source="{http://www.ni.com/LabVIEW.FPGA/SystemDesigner/SystemModel}LocalFifo">
......
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